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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Pin Description
PIN
1, 31
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19, 25, 30,
34–39, 42, 48
20, 24
21, 22, 23
26
27
28
29
32, 33, 47
40
41
43
44
45
46
—
NAME
DGND
OPSAFE1
A0/ CS
CNVST
SPI/ I2C
ALARM
OPSAFE2
REFDAC
REFADC
DXP1
DXN1
DXP2
DXN2
ADCIN1
ADCIN2
PGAOUT2
GATE2
GATE1
N.C.
AV DD
AGND
CS2+
CS2-
CS1-
CS1+
DV DD
PGAOUT1
A2/N.C.
SCL/SCLK
SDA/DIN
A1/DOUT
BUSY
EP
FUNCTION
Digital Ground. Connect both DGND inputs to the same potential.
Output Safe Switch Logic Input 1. Drive OPSAFE1 high to close the output safe switch and clamp
GATE1 to AGND. Drive OPSAFE1 low to open the switch.
Address-Select Input 0/Chip-Select Input. In I 2 C mode, this is the address-select input 0. See Table
1. In SPI mode, this is the chip-select input.
Active-Low Conversion Start Input. Drive CNVST low to begin a conversion when in clock modes 01
and 11.
Interface-Select Input. Connect to DGND for I 2 C interface. Connect to DV DD for SPI interface.
Alarm Output
Output Safe Switch Logic Input 2. Drive OPSAFE2 high to close the output safe switch and clamp
GATE2 to AGND. Drive OPSAFE2 low to open the switch.
DAC Reference Input/Output
ADC Reference Input/Output
Temperature Diode Positive Input 1. Connect DXP1 to the anode of the external diode.
Temperature Diode Negative Input 1. Connect DXN1 to the cathode of the external diode.
Temperature Diode Positive Input 2. Connect DXP2 to the anode of the external diode.
Temperature Diode Negative Input 2. Connect DXN2 to the cathode of the external diode.
ADC Auxiliary Input 1
ADC Auxiliary Input 2
Programmable-Gain Amplifier Output 2
Gate-Drive Amplifier Output 2
Gate-Drive Amplifier Output 1
No Connection. Not internally connected. Leave unconnected.
Analog-Supply Input. Connect both AV DD inputs to the same potential.
Analog Ground. Connect all AGND inputs to the same potential.
Current-Sense Positive Input 2. CS2+ is the external sense-resistor connection to the LDMOS 2 supply.
Current-Sense Negative Input 2. CS2- is the external sense-resistor connection to the LDMOS 2 drain.
Current-Sense Negative Input 1. CS1- is the external sense-resistor connection to the LDMOS 1 drain.
Current-Sense Positive Input 1. CS1+ is the external sense-resistor connection to the LDMOS 1 supply.
Digital-Supply Input. Connect all DV DD inputs to the same potential. Connect a 0.1μF capacitor to
DV DD .
Programmable-Gain Amplifier Output 1
Address-Select Input 2/N.C. In I 2 C mode, this pin is the address-select input 2. See Table 1. In SPI
mode, this is a no connection pin.
Serial-Clock Input. SCL is the I 2 C-compatible clock input. SCLK is the SPI-compatible clock input.
Serial-Data Input/Output. SDA is the I 2 C-compatible input/output. DIN is the SPI-compatible data input.
Address-Select Input 1/Data Out. In I 2 C mode, this is the address-select input 1. See Table 1. In SPI
mode, this is the serial-data output. Data is clocked out on the falling edge of SCLK. DOUT is a high-
impedance output when CS is driven high.
Busy Output. BUSY goes high to indicate activity.
Exposed Pad. Connect EP to AGND. Internally connected to AGND.
______________________________________________________________________________________
13
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